This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
The traditional transistor includes a channel, which conducts current between a source and a drain, and a gate which controls flow of that current through the channel. Transistors are generally termed field effect transistors, or FETs. There are two predominant types depending on the type of dopant used in their fabrication: n-FETs and p-FETs. While there are many variations applicable to either type, including FinFETs which increase electron and hole mobility in the channel, and multi-gate structures which better control the current, this general paradigm holds true for them all.
As transistors have become smaller in size and the currents they convey become commensurately smaller, it has become more important to control for current leakage via the semiconductor substrate which lies below the channel by disposing the gate on more than simply the top surface of the channel as was done with early transistors. The most effective gate control is therefore disposing the gate fully about the cross sectional profile of the channel. This is shown at FIG. 1A. The channel 10 is shown as a nanowire reflecting its small diameter, on the order of tens of nanometers or less. This is fully enveloped by the polysilicone gate 14 with an interstitial layer of gate oxide 12 lying there between to enhance electrical coupling of the gate material 14 to the channel 10. FIG. 1B is a micrograph showing a sectional view of multiple beams which are a part of the same channel. FIG. 1C is a micrograph showing a plan view of a transistor with source, gate and drain labeled; current flows from source to drain through a channel that lies under the illustrated gate. FIG. 1D is the cross-section through the gate from micrograph in FIG. 1C. The channel 10 is shown and the gate dielectric and gate are illustrated as a combined gate stack 16.
It is noted that the wire which forms a transistor channel 10 is not restricted to the circular shape of a traditional wire as FIGS. 1A-1D illustrate; it is common to employ rectilinear channels with definite sidewall, top and bottom surfaces against which the gate and gate oxide is disposed. Representative but non-limiting dimensions for such rectilinear nanowires are on the order of 20 nm or less wide and thick. The gate length will be determined by the application of the nanowire device and can range from 5 nm to a few microns. The gate oxide or other gate dielectric would be disposed at a thickness on the order of about a few nanometers at most and the gate itself would run to a thickness of no more than 100 nm. Such dimensions are operable for both n-FET and p-FET devices.
The continuing reduction is transistor size results in the need for better gate control and for more precise metering of smaller and smaller currents. Nano-scale channels and gates are being developed to satisfy the need for smaller physical size. What is needed is a more effective electrical conduit for the channel to meet increasingly stringent demands of speed and slight current.